1. Field of the Invention
Embodiments of the present invention relate generally to network processors, switches, routers, networks, and pipeline optimization methods and, in specific embodiments, to a network processor with a processing pipeline.
2. Related Art
With the increasing use of the Internet for data intensive applications, there has been a growing demand for greater communication speeds. While communication links, such as fiber optic cables, are able to support high communication rates, overall communication speed has been limited by the speed of processors used to process data transmitted over the communication links. Recently, there has been a recognition that general purpose processors cannot process packets fast enough to keep up with the demand for greater network speeds. Thus, a new type of specialized processor, known as a “network processor”, has emerged to perform packet processing operations with improved performance.
A related art network processor is disclosed in U.S. Pat. No. 6,778,534 entitled “High-Performance Network Processor”, the contents of which are incorporated by reference herein, and which is hereinafter referred to as reference 1. FIG. 1 illustrates a design of a network processor 120 as disclosed in reference 1. A key feature of the network processor 120 is the use of task optimized processors (TOPs) 122, 123, 124, and 125, which are employed in a pipelined architecture, to perform the packet processing tasks of parse, search, resolve, and modify. Each TOP 122, 123, 124, 125 may be configured with a customized instruction set and a customized data path for performing specific tasks, so as to reduce a number of clock cycles required to complete the tasks as compared with general purpose processors. The pipelined architecture serves as a sort of computing assembly line in which processing of different packets at different stages of the pipeline can occur at a same time.
As described in reference 1, and with reference to FIG. 1, information packets from a network 110 are transferred to a parsing stage TOP 122 of the network processor 120 via a link controller 121. The parsing stage TOP 122 allows for extracting and analyzing the contents of packet headers and fields. From the parsing stage TOP 122, packets are passed to a searching stage TOP 123, which also receives search keys extracted by the parsing stage TOP 122. The searching stage TOP 123 performs various table look-ups required for switching, routing, session switching, content switching, and policy enforcement. Search results from the searching stage TOP 123 are then passed along with the packet to a resolution stage TOP 124, which assigns the packet to an appropriate output port, and attends to any quality of service requirements. From the resolution stage TOP 124, the packet is passed to a modification stage TOP 125, where the modification stage TOP 125 allows for modifying certain fields within the packet. The packet is then queued in a queue 126, and then output to a switch matrix 130. Each of the TOPs 122, 123, 124, 125 is able to access random access memory (RAM) 127.
A comparison is provided in reference 1 of clock cycles required to perform packet processing tasks using TOPs versus clock cycles required to perform the same tasks by a general purpose processor. For example, while a typical general purpose processor may take 400 clock cycles to parse a typical HTTP packet and determine a URL, a parser implemented as a TOP may take only 60 clock cycles. Also, while a general purpose processor may take 80 clock cycles to resolve a multicast routing decision, a TOP may take 8 or less clock cycles. Thus, substantial performance improvements are realized through the use of task optimized processors.
Another related art network processor is disclosed in U.S. Pat. No. 7,075,926 entitled “Programmable Packet Processor with Flow Resolution Logic”, the contents of which are incorporated by reference herein, and which is hereinafter referred to as reference 2. FIG. 2 illustrates a network processor 200 as disclosed in reference 2. A key feature of the network processor 200 is a packet classification engine 220 that classifies each input packet by packet type using one or both of header data and payload data, and then identifies application programs to be executed by sub-engines 231, 232, 233, and 234 based on the determined packet type. The sub-engines 231, 232, 233, 234 are packet processing engines that are arrayed in a pipelined architecture and, thus, are configured to process inbound packets in stages.
As described in reference 2, and with reference to FIG. 2, an input packet is stored in packet buffer 210, and the packet classification engine 220 identifies programs to be executed by each sub-engine 231, 232, 233, 234 in an application engine 230 based on a determined packet type of the input packet. The packet classification engine 220 then provides start indicators to indicate start addresses of the programs to be executed by the sub-engines 231, 232, 233, 234. A first sub-engine 231 in the pipeline starts executing an associated program at an associated start address specified by the packet classification engine 220 and, once the execution of the associated program has completed, the first sub-engine 231 starts the next sub-engine 232 in the pipeline. The process continues until the last sub-engine 234 in the pipeline has executed its associated program, where the associated program starts at an associated start address provided by the packet classification engine 220. Thus, in the network processor 200, programs to be executed by pipelined sub-engines 231, 232, 233, 234 for processing a packet are determined based on a classified type of the packet.
Examples of further related art systems and methods are disclosed in the following references: (i) U.S. Provisional App. Ser. No. 60/206,617, entitled “System and Method for Enhanced Line Cards”; (ii) U.S. Provisional App. Ser. No. 60/206,996, entitled “Flow Resolution Logic System and Method”; (iii) U.S. Provisional App. Ser. No. 60/220,335, entitled “Programmable Network Processor”; (iv) U.S. Provisional App. Ser. No. 60/246,447, entitled “High Speed Network Processor”; (v) U.S. Provisional App. Ser. No. 60/278,310, entitled “Non-Blocking Multi-Context Pipelined Processor”; (vi) U.S. Pat. No. 7,080,238, entitled “Non-Blocking Multi-Context Pipelined Processor”; (vii) U.S. Pat. No. 6,996,117, entitled “Vertical Instruction and Data Processing in a Network Processor Architecture”; and (viii) U.S. Pat. No. 7,010,673, entitled “Apparatus and Method for Processing Pipelined Data”; the contents of each of which are incorporated by reference herein.